1. Field of the Invention
The present invention relates to a ceramic multilayer wiring substrate in which the electrical resistance values of the signal lines to a semiconductor chip are partially changed in the same plane or on the same substrate.
2. Description of the Prior Art
It is generally known that if the electrical resistivity of specific metal wirings from a group of metal wirings is altered, the electrical characteristics of a semiconductor chip can be maximized. The electrical resistance is altered to solve various electrical problems such as switching noise (ex. "ringing", "voltage input high") and the like generated during the operation of the semiconductor chip mounted thereon. For example, to reduce switching noises, one must establish matching impedance between the semiconductor chip and the multilayer wiring substrate. In order to satisfy this requirement, the electrical resistivity of the metallic wirings to which the chip is connected must be altered. Such adjustments of resistivity can also compensate for advancements on the semiconductor itself with respect to density of integration and operational speed (frequency).
Conventionally, if the electrical resistivities of a specific number of metallized wirings were to be changed, two approaches were available: (a) generally, the width of each affected metallized wiring would be changed, or (b) a resistor would be added in the wiring circuit to the outside of the ceramic multilayer wiring substrate or embedded in the substrate if necessary.
In improving the density of integration and the operational speed (frequency) of a semiconductor chip, several of these problems are brought to the foreground.
In the first approach, the width of the metallized wirings is altered. However, as semiconductor chips are improved with respect to density of integration and operational speed, they require still more metallized wirings than are currently utilized. The multilayer substrate is of limited size and can accommodate only a certain total area of metallized wirings. Thus, as chip technology advances, there is a limit to which this method may address that technology. Moreover, adding additional metallized wirings and/or changing the spatial configuration of the wirings alters the electrical characteristics of the wirings (e.g. capacitance) This is not necessarily a beneficial change.
The second approach or method for changing the electrical resistivity of the metallized wirings involves the use of a resistor either above the surface or embedded into the surface of the multilayer wiring substrate. The reliability and durability of this addition is poor. Moreover, production costs are increased, because the addition of the resistor(s) requires additional materials and manufacturing steps.